Hardware Interrupt - Fujitsu F2MC-16LX Hardware Manual

3.4

Hardware Interrupt

Hardware interrupt is a function to temporarily stop the execution of program being
executed by the CPU in response to an interrupt request signal from the peripheral
function. It then moves control to the interrupt processing program defined by a user.
Also, µ µ µ µ DMA/Eextended intelligent I/O service (EI
executed as a kind of hardware interrupt.
I Hardware interrupt function
❍ Hardware interrupt function
A hardware interrupt compares the interrupt level of an interrupt request signal that is output by
the peripheral function and interrupt level mask register (ILM) in the CPU processor status (PS).
It then refers to the I-flag in the processor status (PS) to determine whether or not the interrupt
is acceptable.
If the hardware interrupt is accepted, registered contents in the CPU are automatically stored to
the system stack, and the interrupt level currently requested is saved in the interrupt level mask
register (ILM). In this event, control then branches to the corresponding interrupt vector.
❍ Multiple interrupts
Multiple hardware interrupts can start at one time.
❍ µ µ µ µ DMA/Extended intelligent I/O service (EI
µDMA/Extended intelligent I/O service (EI
memory and I/O, and if the transfer is completed, a hardware interrupt starts. µDMA/Extended
intelligent I/O service (EI
is executed, other interrupt requests and all µDMA/Extended intelligent I/O service (EI
requests wait temporarily.
❍ External interrupt
An external interrupt (including wake-up interrupt) is accepted as a hardware interrupt via the
peripheral function (interrupt request detect circuit).
❍ Interrupt vector
Interrupt processing refers to the interrupt vector table assigned in memory addresses ranging
from "FFFC00
For the assignment of interrupt number and interrupt vector, see Section 3.2 "Interrupt Factor
and Interrupt Vector".
2
OS) does not start in a multiplex manner, and if some µDMA process
" to "FFFFFF " and shared with software interrupts.
H H
2
OS) external interrupt may be
2
OS)
2
OS) is an automatic transfer function between
CHAPTER 3 INTERRUPT
2
OS)
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