Fujitsu F2MC-16LX Hardware Manual page 67

• At a read
Figure 3.3-2 Interrupt Control Registers (ICR00 to ICR15) during Reading
Address Bit 7 6
0000B0
H
to
0000BF
H
: Initial value
5 4 3 2 1
S0 ISE IL2 IL1
S1
IL2
0
0
0
0
1
1
1
1
ISE
0
1
S1
0
0
1
1
0
Initial value
IL0
X X 0 0 0 1 1 1
B
Interrupt level setting bit
IL1 IL0
0 0
Interrupt level 0 (highest)
0 1
1 0
1 1
0 0
0 1
1 0
Interrupt level 7 (no interrupt)
1 1
2
EI OS activate bit
Activates the interrupt sequence when an interrupt occurs
2
Activates EI OS when an interrupt occurs
2
EI OS status
S0
2
0
EI OS operation in progress or EI
1 Stopped status due to count termination
0 Reserved
1
Stopped status due to a request from the peripheral function
CHAPTER 3 INTERRUPT
(when µDMA is used)
2
OS not activated
51