Interrupt By Μdma - Fujitsu F2MC-16LX Hardware Manual

Interrupt by µ µ µ µ DMA
3.6
The µ µ µ µ DMA controller is a simplified DMA that has the same function as EI
transfers are set up using the EI
I µ µ µ µ DMA functions
µDMA has the functions listed below.
• Provides an automatic data transfer between a peripheral resource (I/O) and memory.
• CPU program execution stops during the DMA start sequence.
• A DMA transfer channel has 16 channels (a smaller channel number is assigned a higher
DMA transfer priority)
• Allow selection of whether or not to increment the transfer source, transfer destination
addresses.
• A DMA transfer starts with an interrupt factor of the peripheral resource (I/O).
• DMA transfers are controlled with a (a) DMA enable register, (b) DMA stop status register,
(c) DMA status register and (e) descriptor (assigned to a range of 000100
RAM).
• STOP requests are issued as a means to stop DMA transfers from a resource.
• After the end of a DMA transfer, a flag is set to the bit corresponding to the transfer end
channel of the DMA status register, and an end interrupt is then output to the interrupt
controller.
2
OS descriptor.
CHAPTER 3 INTERRUPT
2
OS. DMA
to 00017F
H H
69
in