Chip Selection Control Register (Cscr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 23 CHIP SELECTION FACILITY

23.2.3 Chip Selection Control Register (CSCR)

This section describes the configuration and functions of the chip selection control
register (CSCR).
I Chip selection control register (CSCR)
The diagram below shows the bit configuration of the chip selection control register (CSCR).
0000C8
H
[Bit 7-4] Unused bits
These bits are unused. In read operations, the return value for these bits is undefined.
[Bit 3-0] OPL3-0
These bits are used to specify whether CS3-0 are output to the external pin.
The operational settings are as follows:
• "0": Decode output from each CS3-0 pin is prohibited
• "1": Decode output from each CS3-0 pin is allowed
Note:
• The initial value of OPL0 is set to "1" in external vector mode, and set to "0" in internal vector
mode.
• Enabling or disabling CS3-0 output must be performed after all settings have been made.
• Change settings during operation only after prohibiting output.
444
7 6 5 4
- - - -
(-) (-) (-) (-)
(-) (-) (-) (-)
3 2 1 0
OPL3 OPL2 OPL1 OPL0
(R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (*)
CSCR
Chip selection control register
Read/write
Initial value