Fujitsu F2MC-16LX Hardware Manual page 66

CHAPTER 3 INTERRUPT
• At a write
Figure 3.3-1 Interrupt Control Registers (ICR00 to ICR15) during Writing
Address
Bit
0000B0
H
ICS3 ICS2 ICS1
to
0000BF
H
: Initial value
50
7 6 5 4 3
ICS0 ISE
2 1 0 Initial value
IL2 IL1 IL0
0 0 0 0 0 1 1 1
IL2 IL1 IL0 Interrupt level setting bit
0 0 0
Interrupt level 0 (highest)
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Interrupt level 7 (no interrupt)
1 1 1
2
EI OS activate bit
ISE
Activates the interrupt sequence when an interrupt occurs
0
2
1
Activates EI OS when an interrupt occurs
ICS3 ICS2 ICS1 ICS0
Channel
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
B
(when µDMA is used)
2
EI OS channel setting bit
Descriptor address
100h
108h
110h
118h
120h
128h
130h
138h
140h
148h
150h
158h
160h
168h
170h
178h