Counter Control Register H0 (Ccrh0) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER

13.2.1 Counter control register H0 (CCRH0)

This section shows the configuration and explains the function of counter control
register H0 (CCRH0).
I Counter control register H0 (CCRH0)
The bit configuration of counter control register H0 (CCRH0) is shown below.
Figure 13.2-2 Bit configuration of counter control register H0 (CCRH0)
Bit
CCRH0
Address: 00006D
Counter control register H0 (CCRH0) consists of bits that have the functions explained below.
[Bit 15] M16E (16-bit mode permit)
This bit is used to select (switch) an operation mode of 8 bits x 2 channels or 16 bits x 1
channel.
M16E
0
1
If this bit is rewritten after its start, the count value is not assured.
[Bit 14] CDCF (count direction reversal flag)
This bit is a flag that is set when the count direction is switched. It is set in the count start
mode when the count direction is switched from either up to down or down to up.
Only writing "0" is permitted, and "1" cannot be written.
Read-modify-write type instructions return "1" irrespective of bit values.
CDCF
0
1
[Bit 13] CFIE (count direction reversal interrupt enable)
If CDCF is defined, this bit is used to control interrupt output to the CPU. An interrupt is
generated if count direction changes even a single time in the count start mode.
CFIE
0
1
254
15 14 13 12
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 00000000
H
R/W R/W R/W R/W R/W
Setting 16-bit mode permit
8 bits x 2 channels operation mode (initial value)
16 bits x 1 channel operation mode
Direction reversal detection
No reversal of direction (initial value)
One or more reversals of direction
Direction reversal interrupt output
Direction reversal interrupt output prohibit (initial value)
Direction reversal interrupt output permit
11 10 9 8
R/W R/W R/W
Initial value
B