Ppg0/2/4 Operation Mode Control Register (Ppgc0) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 17 8/16-BIT PPG TIMER

17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0)

This section describes the configuration and functions of the PPG0/2/4 operation
mode control register (PPGC0).
I PPG0/2/4 operation mode control register (PPGC0)
The PPG0/2/4 operation mode control register (PPGC0) is used to select the channel 0/2/4
operation mode, control the pin output, select the count clock, and control the trigger.
The bit configuration of the PPG0/2/4 operation mode control register (PPGC0) is shown below.
7
00003A
H
00003C
PEN0
H
00003E
H
(R/W)
(0)
The functions of the PPG0/2/4 operation mode control register (PPGC0) are described below.
[Bit 7] PEN0: ppg Enable (operation enable)
This bit is used to start PPG operation and select the operation mode.
PEN0
0
1
• With this bit is set to "1", the PPG starts counting.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[Bit 5] PE00: ppg output enable 00 (PPG0/2/4 output pin enable)
This bit is used to allow/prohibit pulse output via the pulse output external pin PPG0/2/4.
PE00
0
1
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
334
6 5 4 3
- PE00 PIE0 PUF0
(-) (R/W) (R/W) (R/W)
(X) (0) (0) (0)
Operation state
Operation stop ("L" level output is retained)
PPG operation enable
Operation state
General-purpose support pin (pulse output prohibited)
PPG0/2/4 pulse output (pulse output allowed)
2 1 0 PPGC0/2/4
- - Reserved Operation mode control register
(-) (-) (-) Reading/writing
(X) (X) (1) Initial value