Fujitsu F2MC-16LX Hardware Manual page 227

Figure 10.4-2 Clearing times and interval time of watchdog timer
[Block diagram of watchdog timer]
[Minimum interval time] The WTE bit is cleared immediately before the count clock starts.
Counter clearing
Count clock a
frequency divide-by-2 value b
frequency divide-by-2 value c
Count permit
Reset signal d
[Maximum interval time] The WTE bit is cleared immediately after the count clock starts.
Counter clearing
Count clock a
frequency divide-by-2 value b
frequency divide-by-2 value c
Count permit
Reset signal d
WTE bit clearing
2-bit counter
frequency
a b
Clock
divide-by-2
selector
circuit
Count permit
output circuit
WTE bit
Start of count
7 × (count-clock-cycles/2)
WTE bit clearing
Start of count
9 × (count-clock-cycles/2)
CHAPTER 10 WATCHDOG TIMER
frequency
c
Reset circuit
divide-by-2
circuit
Count permit and clear
Occurrence of watchdog reset
Occurrence of watchdog reset
d
Reset signal
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