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13.3.1 Counter control register (ch.0) upper (CCRH0)
This section shows the configuration and explains the functions of counter control
register (ch.0) upper (CCRH0).
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Counter control register (ch.0) upper (CCRH0)
The bit configuration of counter control register (ch.0) upper (CCRH0) is shown below.
Figure 13.3-2 Bit configuration of counter control register (ch.0) upper (CCRH0)
CCRH0
ch.0 Address: 00006D
Counter control register (ch.0) upper (CCRH0) consists of bits that have the functions explained
below.
[bit15] M16E (16-bit mode permit)
This bit is used to select (switch) an operation mode of 8 bits x 2 channels or 16 bits x 1
channel.
M16E
0
1
If this bit is rewritten after its start, the count value is not assured.
[bit14] CDCF (count direction reversal flag)
This bit is a flag that is set when the count direction is switched. It is set in the count start
mode when the count direction is switched from either up to down or down to up.
The initialization (writing "0") is only permitted.
Read-modify-write type instructions read "1" irrespective of bit values.
CDCF
0
1
[bit13] CFIE (count direction reversal interrupt enable)
If CDCF is defined, this bit is used to control interrupt output to the CPU. An interrupt occurs if
count direction changes even a single time in the count start mode when this bit is set to "1".
bit
15
14
13
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 00000000
H
R/W
R/W
R/W R/W R/W
8 bits x 2 channels operation mode (initial value)
16 bits x 1 channel operation mode
No reversal of direction (initial value)
One or more reversals of direction
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
12
11
10
9
R/W
R/W R/W
Setting 16-bit mode permit
Direction reversal detection
8
Initial value
B
265
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