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Timing Requirements
4.2
CLK domain
4-4
The timings for the CLK domain signals are shown in Figure 4-2.
The timing requirements for the CLK domain signals are listed in Table 4-2. All figures
are expressed as percentages of the CLK period at maximum operating frequency.
Note
A 0% figure in Table 4-2 indicates the hold time to clock edge plus the maximum clock
skew for internal clock buffering.
Parameter
T
ovctrans
T
ohctrans
T
ovmbdtrans
T
ohmbdtrans
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Table 4-2 CLK domain timing requirements
Description
Rising CLK to CLK domain outputs valid
CLK domain outputs hold time from CLK rising
Rising CLK to MBISTDOUT output valid
MBISTDOUT output hold time from CLK
rising
Figure 4-2 CLK domain signals
Max
40%
60%
-
ARM DDI 0275D
Min
-
>0%
-
>0%
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