Table 5.23 Displayed Contents Of The Help Display Area For Menu Selection - Fujitsu PRIMEQUEST 1000 Series Tool Reference

PRIMEQUEST 1000 Series Tool Reference
CHAPTER 5 UEFI Menu Operations

TABLE 5.23 Displayed contents of the help display area for menu selection

Cursor position
Enhanced Speed Step
Turbo Boost Technology
Performance/Watt
Enhanced Idle Power State
ACPI C3 State
Hyper Threading
Active Processor Cores
Virtualization Technology (VT-x)
Virtualization Technology (VT-d)
Adjacent Cache Line Prefetch
Hardware Prefetch
x2APIC Mode
Commit Changes and Exit
Discard Changes and Exit
Displayed contents
Enhanced Intel SpeedStep Technology centralizes the control
mechanism in the processor, eliminating the need for
coordination with the chip set during the frequency/voltage
transition.
When 'Enabled', a processor has the ability to run at frequencies
higher than the advertised frequency of the part when requested
and when operating conditions allow higher frequency.
When 'Power Optimized' is selected Intel Turbo Boost
Technology engages after performance state P0 is sustained for
more than 2 seconds. When 'Traditional' is selected Intel Turbo
Boost Technology is engaged even for P0 requests less than 2
seconds.
When 'Enabled', a processor consumes lower power than C1
state.
Enables the C3 state.
When 'Disabled' only one thread per enabled core is enabled.
[PRIMEQUEST 1800E only, SA11031 or earlier]
Each bit position represents a core to be enabled in each
processor package.
[PRIMEQUEST 1800E SA11051 or later and PRIMEQUEST
1800E2]
Number of cores to enable in each processor package.
When enabled, a VMM can utilize the additional hardware
capabilities provided by Intel(R) Virtualization Technology.
VT-d enables direct assignment of PCI devices to a virtual
machines.
When enabled the processor fetches both cache lines that
comprise a cache line pair (128 bytes) when it determines
required data is not currently in its cache. When disabled the
processor will only fetch the cache line (64 bytes) that contains
the data currently required by the processor.
When enabled processor assumes that if line A and A+1 were
required, then line A+2 also will be required. The data is
prefetched into L2 from external memory.
When Disabled, x2APIC mode is disabled.
Nothing
Nothing
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