Instruction Cache Synonyms - IBM PPC440X5 CPU Core User Manual

User's Manual
Preliminary PPC440x5 CPU Core
At this point, software may begin executing the instruction at addr1 and be guaranteed that the new instruc-
tion will be recognized.

4.2.3.2 Instruction Cache Synonyms

A synonym is a cache line that is associated with the same real address as another cache line that is in the
cache array at the same time. Such synonyms can occur when different virtual addresses are mapped to the
same real address, and the virtual address is used either as an index to the cache array (a virtually-indexed
cache) or as the cache line tag (a virtually-tagged cache).
The instruction cache on the PPC440x5 is real-indexed but virtually-tagged and thus it is possible for
synonyms to exist in the cache. (The data cache on the other hand is both real-indexed and real-tagged, and
thus cannot have any synonyms.) Because of this, special care must be taken when managing instruction
cache coherency and attempting to invalidate lines in the cache.
As explained in Memory Management on page 133, the virtual address (VA) consists of the 32-bit effective
address (EA; for instruction fetches, this is the address calculated by the instruction unit and sent to the ICC)
combined with the 8-bit Process ID (PID) and the 1-bit address space (MSR[IS] for instruction fetches). As
described in Table 4-2 on page 96, and using the 32KB cache as an example, VA chooses the byte
27:31
offset within the cache line, while VA is used as the index to select a set, and then the rest of the virtual
23:26
address is used as the tag. The tag thus consists of EA , the PID, and MSR[IS] (for instruction fetches; for
0:22
cache management instructions such as icbi, MSR[DS] is used to specify the address space; see the instruc-
tion descriptions for the instruction cache management instructions for more information). The tag portion of
the VA is compared against the corresponding tag fields of each cache line within the way selected by
VA .
23:26
Note that the address translation architecture of PowerPC Book-E is such that the low-order address bits
22:31 are always the same for the EA, VA, and real address (RA), because these bits are never translated
due to the minimum page size being 1KB (these low-order 10 bits are always used for the byte offset within
the page). As the page size increases, more and more low-order bits are used for the byte offset within the
page, and thus fewer and fewer bits are translated between the VA and the RA (see Table 5-3 on page 142).
Synonyms only become possible when the system-level memory management software establishes multiple
mappings to the same real page, which by definition involves different virtual addresses (either through differ-
ences in the higher-order EA bits which make up the VA, or through different process IDs, or different
address spaces, or some combination of these three portions of the VA).
A further requirement for synonyms to exist in the instruction cache is for more than one of the virtual pages
which map to a given real page to have execute permission, and for these pages to be cacheable (cache
lines associated with pages without execute permission, or for which the caching inhibited storage attribute is
set, cannot be placed in the instruction cache).
If the system-level memory management software permits instruction cache synonyms to be created, then
extra care must be taken when attempting to invalidate instruction cache lines associated with a particular
address. If software desires to invalidate only the cache line which is associated with a specific VA, then only
a single icbi instruction need be executed, specifying that VA. If, however, software wishes to invalidate all
instruction cache lines which are associated with a particular RA, then software must issue an icbi instruction
for each VA which has a mapping to that particular RA and for which a line might exist in the instruction
cache. In order to do this, the memory management software must keep track of which mappings to a given
RA exist (or ever existed, if a mapping has been removed but cache lines associated with it might still exist),
so that icbi instructions can be executed using the necessary VAs.
cache.fm.
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