Register Types; General Purpose Registers; Special Purpose Registers; Condition Register - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core Preliminary

2.2.1 Register Types

There are five register types contained within and/or supported by the PPC440x5 core. Each register type is
characterized by the instructions which are used to read and write the registers of that type. The following
subsections provide an overview of each of the register types and the instructions associated with them.

2.2.1.1 General Purpose Registers

The PPC440x5 core contains 32 integer general purpose registers (GPRs); each contains 32 bits. Data from
the data cache or memory can be loaded into GPRs using integer load instructions; the contents of GPRs can
be stored to the data cache or memory using integer store instructions. Most of the integer instructions refer-
ence GPRs. The GPRs are also used as targets and sources for most of the instructions which read and write
the other register types.
Integer Processing on page 71 provides more information on integer operations and the use of GPRs.

2.2.1.2 Special Purpose Registers

Special Purpose Registers (SPRs) are directly accessed using the mtspr and mfspr instructions. In addi-
tion, certain SPRs may be updated as a side-effect of the execution of various instructions. For example, the
Integer Exception Register (XER) (see Integer Exception Register (XER) on page 72) is an SPR which is
updated with arithmetic status (such as carry and overflow) upon execution of certain forms of integer arith-
metic instructions.
SPRs control the use of the debug facilities, timers, interrupts, memory management, caches, and other
architected processor resources. Table 10-2 on page 454 shows the mnemonic, name, and number for each
SPR, in order by SPR number. Each of the SPRs is described in more detail within the section or chapter
covering the function with which it is associated. See Table 2-3 on page 50 for a cross-reference to the asso-
ciated document section for each register.

2.2.1.3 Condition Register

The Condition Register (CR) is a 32-bit register of its own unique type and is divided up into eight, indepen-
dent 4-bit fields (CR0–CR7). The CR may be used to record certain conditional results of various arithmetic
and logical operations. Subsequently, conditional branch instructions may designate a bit of the CR as one of
the branch conditions (see Branch Processing on page 64). Instructions are also provided for performing
logical bit operations and for moving fields within the CR.
See Condition Register (CR) on page 67 for more information on the various instructions which can update
the CR.
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