Data Address Compare Registers (Dac1-Dac2); Data Value Compare Registers (Dvc1-Dvc2); Figure 8-5. Instruction Address Compare Registers (Iac1-Iac4); Figure 8-6. Data Address Compare Registers (Dac1-Dac2) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
0
Figure 8-5. Instruction Address Compare Registers (IAC1–IAC4)
0:29 Instruction Address Compare (IAC) word address
30:31 Reserved
8.6.6 Data Address Compare Registers (DAC1–DAC2)
The two DAC registers specify the addresses upon which DAC (and/or DVC) debug events should occur.
Each of the DAC registers can be written from a GPR using
0
Figure 8-6. Data Address Compare Registers (DAC1–DAC2)
0:31 Data Address Compare (DAC) byte address
8.6.7 Data Value Compare Registers (DVC1–DVC2)
The DVC registers specify the data values upon which DVC debug events should occur. Each of the DVC
registers can be written from a GPR using
0
Figure 8-7. Data Value Compare Registers (DVC1–DVC2)
0:31 Data value to compare
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mtspr , and can be read into a GPR using mfspr .
mtspr , and can be read into a GPR using mfspr .
Preliminary
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debug.fm.
September 12, 2002