Dcbst - IBM PPC440X5 CPU Core User Manual

dcbst

Data Cache Block Store
PPC440x5 CPU Core User's Manual
dcbst
Data Cache Block Store
dcbst RA, RB
31
0 6
EA (RA|0) + (RB)
DCBST(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0, and is the contents of register RA otherwise.
If the data block at the EA is in the data cache and marked as modified, the data block is copied back to main
storage and marked as unmodified in the data cache.
If the data block at the EA is in the data cache, and is not marked as modified, or if the data block at the EA is
not in the data cache, no operation is performed.
The operation specified by this instruction is performed whether or not the memory page referenced by the
EA is marked as cacheable.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Exceptions
This instruction is considered a "load" with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
This instruction is considered a "store" with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.
Page 298 of 589
RA RB
11 16
54
21
September 12, 2002
Preliminary
31
instrset.fm.