Srawi - IBM PPC440X5 CPU Core User Manual

Preliminary

srawi

Shift Right Algebraic Word Immediate
srawi RA, RS, SH
srawi. RA, RS, SH
31
0 6
n SH
r ROTL((RS), 32 – n)
m MASK(n, 31)
s (RS)
0
32
(RA) (r m) (
XER[CA] s ((r
The contents of register RS are shifted right by the number of bits specified in the SH field. Bits shifted out of
the least significant bit are lost. Bit RS
placed into register RA.
If register RS contains a negative number and any 1-bits were shifted out of the least significant bit position,
XER[CA] is set to 1; otherwise, it is set to 0.
Registers Altered
• RA
• XER[CA]
• CR[CR0] if Rc contains 1
instrset.fm.
September 12, 2002
RS RA
11
s m)
m) 0)
is replicated to fill the vacated positions on the left. The result is
0
Shift Right Algebraic Word Immediate
PPC440x5 CPU Core User's Manual
Rc=0
Rc=1
SH
16 21
srawi
824 Rc
31
Page 407 of 589