Mcrxr - IBM PPC440X5 CPU Core User Manual

Preliminary

mcrxr

Move to Condition Register from XER
mcrxr BF
31
0 6
n BF
(CR[CRn]) XER
0:3
4
XER 0
0:3
The contents of XER
0:3
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• CR[CRn] where n is specified by the BF field.
• XER[SO, OV, CA]
Invalid Instruction Forms
• Reserved fields
instrset.fm.
September 12, 2002
BF
9
are placed into the CR field specified by the BF field. XER
Move to Condition Register from XER
PPC440x5 CPU Core User's Manual
512
21
are then set to 0.
0:3
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mcrxr
31