Dbsr; Figure 10-12. Debug Status Register (Dbsr) - IBM PPC440X5 CPU Core User Manual

DBSR

Debug Status Register
PPC440x5 CPU Core User's Manual
DBSR
SPR 0x130 Supervisor Read/Clear
See Debug Status Register (DBSR) on page 244.
BRT
IDE MRR TRAP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
UDE ICMP IRPT IAC1

Figure 10-12. Debug Status Register (DBSR)

Imprecise Debug Event
0 Debug event ocurred while MSR[DE] = 1
0 IDE
1 Debug event occurred while MSR[DE] = 0
Unconditional Debug Event
0 Event didn't occur
1 UDE
1 Event occurred
Most Recent Reset
00 No reset has occurred since this field was last
2:3 MRR
01 Core reset
10 Chip reset
11 System reset
Instruction Completion Debug Event
0 Event didn't occur
4 ICMP
1 Event occurred
Branch Taken Debug Event
0 Event didn't occur
5 BRT
1 Event occurred
Interrupt Debug Event
0 Event didn't occur
6 IRPT
1 Event occurred
Trap Debug Event
0 Event didn't occur
7 TRAP
1 Event occurred
IAC 1 Debug Event
0 Event didn't occur
8 IAC1
1 Event occurred
IAC 2 Debug Event
0 Event didn't occur
9 IAC2
1 Event occurred
IAC 3 Debug Event
10 IAC3 0 Event didn't occur
1 Event occurred
IAC 4 Debug Event
0 Event didn't occur
11 IAC4
1 Event occurred
DAC 1 Read Debug Event
0 Event didn't occur
12 DAC1R
1 Event occurred
Page 476 of 589
IAC2 IAC4 DAC1W DAC2W
IAC3 DAC1R DAC2R
RET
cleared by software.
For synchronous debug events in internal debug
mode, this field indicates whether the correspond-
ing Debug interrupt occurs precisely or impre-
cisely
This field is set upon any processor reset to a
value indicating the type of reset.
Preliminary
IAC34ATS
29 30 31
IAC12ATS
regsumm440core.fm.
September 12, 2002