Cmpl; Table 9-13. Extended Mnemonics For Cmpl - IBM PPC440X5 CPU Core User Manual

cmpl

Compare Logical
PPC440x5 CPU Core User's Manual
cmpl
Compare Logical
cmpl BF, 0, RA, RB
31
0 6
4
c 0
0:3
u
if (RA) (RB) then c
<
u
if (RA) (RB) then c
>
if (RA) (RB) then c
=
c XER[SO]
3
n BF
CR[CRn] c
0:3
The contents of register RA are compared with the contents of register RB, using a 32-bit unsigned compare.
The CR field specified by the BF field is updated to reflect the results of the compare and the value of
XER[SO] is placed into the same CR field.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• CR[CR n ] where n is specified by the BF field
Invalid Instruction Forms
• Reserved fields
Programming Notes
PowerPC Book-E Architecture defines this instruction as cmpl BF,L,RA,RB, where L selects operand size
for 64-bit implementations. For all 32-bit implementations, L = 0 is required (L = 1 is an invalid form); hence
for PPC440x5 core, use of the extended mnemonic cmplw BF,RA,RB is recommended.

Table 9-13. Extended Mnemonics for cmpl

Mnemonic Operands
cmplw
[BF,] RA, RB
Page 284 of 589
BF RA
9 11
1
0
1
1
1
2
Compare Logical Word.
Use CR0 if BF is omitted.
Extended mnemonic for
cmpl BF,0,RA,RB
RB
16 21
Function
Preliminary
32
31
Other Registers
Altered
instrset.fm.
September 12, 2002