lhzux
Load Halfword and Zero with Update Indexed
PPC440x5 CPU Core User's Manual
lhzux
Load Halfword and Zero with Update Indexed
lhzux
RT, RA, RB
31
0
6
EA
(RA|0) + (RB)
(RA)
EA
16
(RT)
0 || MS(EA,2)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is
placed into register RA.
The halfword at the EA is extended to 32 bits by concatenating 16 0-bits to its left. The result is placed into
register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• RA
• RT
Invalid Instruction Forms
• Reserved fields
• RA = RT
• RA = 0
Page 332 of 589
RT
RA
11
RB
16
21
Preliminary
311
31
instrset.fm.
September 12, 2002