Overflow (Ov) Field; Carry (Ca) Field; Processor Control - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
2.6.2.2 Overflow (OV) Field
This field is updated by certain integer arithmetic instructions to indicate whether the infinitely precise result of
the operation can be represented in 32 bits. For those integer arithmetic instructions that update XER[OV]
and produce signed results, XER[OV] = 1 if the result is greater than 2
XER[OV] = 0. For those integer arithmetic instructions that update XER[OV] and produce unsigned results
(certain integer divide instructions and multiply-accumulate auxiliary processor instructions), XER[OV] = 1 if
the result is greater than 2
page 249 for more details on the conditions under which the integer divide instructions set XER[OV] to 1.
The mtspr(XER) and mcrxr instructions also update XER[OV]. Specifically, mcrxr sets XER[OV] (and
XER[SO,CA]) to 0 after copying all three fields into CR[CR0]
mtspr(XER) writes XER[OV] with the value in (RS)
XER[OV] is read (along with the rest of the XER) into a GPR by mfspr(XER).

2.6.2.3 Carry (CA) Field

This field is updated by certain integer arithmetic instructions (the "carrying" and "extended" versions of add
and subract) to indicate whether or not there is a carry-out of the most-significant bit of the 32-bit result.
XER[CA] = 1 indicates a carry. The integer shift right algebraic instructions update XER[CA] to indicate
whether or not any 1-bits were shifted out of the least significant bit of the result, if the source operand was
negative (see the instruction descriptions in Instruction Set on page 249 for more details).
The mtspr(XER) and mcrxr instructions also update XER[CA]. Specifically, mcrxr sets XER[CA] (as well as
XER[SO,OV]) to 0 after copying all three fields into CR[CR0]
mtspr(XER) writes XER[CA] with the value in (RS)
XER[CA] is read (along with the rest of the XER) into a GPR by mfspr(XER). In addition, the "extended"
versions of the add and subtract integer arithmetic instructions use XER[CA] as a source operand for their
arithmetic operations.
Transfer Byte Count (TBC) Field
The TBC field is used by the string indexed integer storage access instructions (lswx and stswx) as a byte
count. The TBC field is updated by the dlmzb[.] instruction with a value indicating the number of bytes up to
and including the zero byte detected by the instruction (see the instruction description for dlmzb in Instruction
Set on page 249 for more details). The TBC field is also written by
XER[TBC] is read (along with the rest of the XER) into a GPR by mfspr(XER).

2.7 Processor Control

The PPC440x5 core provides several registers for general processor control and status. These include:
• Machine State Register (MSR)
Controls interrupts and other processor functions
• Special Purpose Registers General (SPRGs)
SPRs for general purpose software use
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32
–1; otherwise, XER[OV] = 0. See the instruction descriptions in Instruction Set on
31
– 1 or less than –2
(and setting CR[CR0]
0:2
.
1
(and setting CR[CR0]
0:2
.
2
mtspr (XER) with the value in (RS)
Preliminary
31
; otherwise,
to 0), while
3
to 0), while
3
.
25:31
prgmodel.fm.
September 12, 2002