Tlb Match Process - IBM PPC440X5 CPU Core User Manual

Preliminary
space, allowing user mode programs running with MSR[IS,DS] set to 1 to access them (system library
routines, for example, which may be shared by multiple user mode and/or supervisor mode programs).
System-level code wishing to use these areas would have to first set the corresponding MSR[IS,DS] field in
order to use the application-level TLB entries, or there would have to be alternative system-level TLB entries
set up.
The net of this is that the notion of application-level code running with MSR[IS,DS] set to 1 and using corre-
sponding TLB entries with the TS=1, and conversely system-level code running with MSR[IS,DS] set to 0 and
using corresponding TLB entries with TS=0, is by convention. It is possible to run in user mode with
MSR[IS,DS] set to 0, and conversely to run in supervisor mode with MSR[IS,DS] set to 1, with the corre-
sponding TLB entries being used. The only fixed requirement in this regard is the fact that MSR[IS,DS] are
cleared on an interrupt, and thus there must be a TLB entry for the system-level interrupt handler code with
TS=0 in order to be able to fetch and execute the interrupt handler itself. Whether or not other system-level
code switches MSR[IS,DS] and creates corresponding system-level TLB entries depends upon the operating
system environment.
Programming Note: Software must ensure that there is always a valid TLB entry with TS=0

5.3.3 TLB Match Process

This virtual address is used to locate the associated entry in the TLB. The address space identifier, the
process identifier, and a portion of the effective address of the storage access are compared to the TS, TID,
and EPN fields, respectively, of each TLB entry.
The virtual address matches a TLB entry if:
• The valid (V) field of the TLB entry is 1, and
• The value of the address space identifier is equal to the value of the TS field of the TLB entry, and
• Either the value of the process identifier is equal to the value of the TID field of the TLB entry (private
page), or the value of the TID field is 0 (globally shared page), and
• The value of bits 0:n–1 of the effective address is equal to the value of bits 0:n-1 of the EPN field of the
TLB entry (where n = 32–log
field of the TLB entry). See Table 5-2 Page Size and Effective Address to EPN Comparison on page 140.
A TLB Miss exception occurs if there is no matching entry in the TLB for the page specified by the virtual
address (except for the tlbsx[.] instruction, which simply returns an undefined value to the GPR file and (for
tlbsx.) sets CR[CR0] to 0). See TLB Search Instruction (tlbsx[.]) on page 153.
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Programming Note: Although it is possible for software to create multiple TLB entries that
mmu.fm.
September 12, 2002
and with supervisor mode execute access permission (SX=1)
corresponding to the effective address of the interrupt handlers.
Otherwise, an Instruction TLB Error interrupt could result upon the fetch
of the interrupt handler for some other interrupt type, and the registers
holding the state of the routine which was executing at the time of the
original interrupt (SRR0/SRR1) could be corrupted. See Interrupts and
Exceptions on page 159 for more information.
(page size in bytes) and page size is specified by the value of the SIZE
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match the same virtual address, doing so is a programming error and the
results are undefined.
User's Manual
PPC440x5 CPU Core
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