Ccr1; Figure 10-2. Core Configuration Register 1 (Ccr1) - IBM PPC440X5 CPU Core User Manual

CCR1

Core Configuration Register 1
PPC440x5 CPU Core User's Manual
CCR1
SPR 0x378 Supervisor R/W
See Core Configuration Register 1 (CCR1) on page 110.
ICDPEI
0
Figure 10-2. Core Configuration Register 1 (CCR1)
Instruction Cache Data Parity Error Insert
0 record even parity (normal)
0:7 ICDPEI
1 record odd parity (simulate parity error)
Instruction Cache Tag Parity Error Insert
0 record even parity (normal)
8:9 ICTPEI
1 record odd parity (simulate parity error)
Data Cache Tag Parity Error Insert
0 record even parity (normal)
10:11 DCTPEI
1 record odd parity (simulate parity error)
Data Cache Data Parity Error Insert
0 record even parity (normal)
12 DCDPEI
1 record odd parity (simulate parity error)
Data Cache U-bit Parity Error Insert
0 record even parity (normal)
13 DCUPEI
1 record odd parity (simulate parity error)
Data Cache Modified-bit Parity Error Insert
14 DCMPEI 0 record even parity (normal)
1 record odd parity (simulate parity error)
Force Cache Operation Miss
0 normal operation
15 FCOM
1 cache ops appear to miss the cache
Memory Management Unit Parity Error Insert
16:19 MMUPEI 0 record even parity (normal)
1 record odd parity (simulate parity error)
Force Full-line Flush
20 FFF 0 flush only as much data as necessary.
1 always flush entire cache lines
21:23 Reserved
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DCTPEI DCUPEI FCOM
7 8 9 10 11 12 13 14 15 16
ICTPEI DCDPEI DCMPEI
FFF
19 20 21 23 24 25
MMUPEI TCS
Controls inversion of parity bits recorded when the
instruction cache is filled. Each of the 8 bits corre-
sponds to one of the instruction words in the line.
Controls inversion of parity bits recorded for the tag
field in the instruction cache.
Controls inversion of parity bits recorded for the tag
field in the data cache.
Controls inversion of parity bits recorded for the
data field in the data cache.
Controls inversion of parity bit recorded for the U
fields in the data cache.
Controls inversion of parity bits recorded for the
modified (dirty) field in the data cache.
Force icbt , dcbt, dcbtst, dcbst, dcbf, dcbi, and
dcbz to appear to miss the caches. The intended
use is with icbt and dcbt only, which will fill a dupli-
cate line and allow testing of multi-hit parity errors.
See Section 4.2.4.7 Simulating Instruction Cache
Parity Errors for Software Testing on page 114 and
Figure 4.3.3.7 on page 130.
Controls inversion of parity bits recorded for the tag
field in the MMU.
When flushing 32-byte (8-word) lines from the data
cache, normal operation is to write nothing, a dou-
ble word, quad word, or the entire 8-word block to
the memory as required by the dirty bits. This bit
ensures that none or all dirty bits are set so that
either nothing or the entire 8-word block is written
to memory when flushing a line from the data
cache. Refer to Section 4.3.1.4 Line Flush Opera-
tions on page 121.
Preliminary
31
regsumm440core.fm.
September 12, 2002