Bcctr; Table 9-9. Extended Mnemonics For Bcctr, Bcctrl - IBM PPC440X5 CPU Core User Manual

Preliminary

bcctr

Branch Conditional to Count Register
bcctr BO, BI
bcctrl BO, BI
19
0 6
if (BO = 1 (CR
0 BI
NIA CTR
0:29
else
NIA CIA + 4
if LK = 1 then
(LR) CIA + 4
PC NIA
If BO contains 0, then the CR bit specified by the BI field is compared to BO
0
If BO contains 1, then the CR is not tested as part of the branch condition, and the BI field is ignored.
0
The next instruction address (NIA) is either the effective address of the branch target, or the address of the
instruction after the branch, depending on whether the branch is taken or not. The branch target address is
formed by concatenating two 0-bits to the right of the 30 most significant bits of the CTR.
BO affects branch prediction, a performance-improvement feature. See Branch Prediction on page 65 for a
4
complete discussion.
Instruction execution resumes with the instruction at the NIA.
If the LK field contains 1, then (CIA + 4) is placed into the LR.
Registers Altered
• LR if LK contains 1
Invalid Instruction Forms
• Reserved fields
• If BO contains 0, the instruction form is invalid, and the result of the instruction (in particular, the branch
2
target address and whether or not the branch is taken) is undefined. The architecture does not permit the
combination of decrementing the CTR as part of the branch condition, together with using the CTR as the
branch target address.

Table 9-9. Extended Mnemonics for bcctr, bcctrl

Mnemonic Operands
bctr
bctrl
instrset.fm.
September 12, 2002
BO BI
11
= BO )) then
1
2
0
Branch unconditionally to address in CTR.
Extended mnemonic for
bcctr 20,0
Extended mnemonic for
bcctrl 20,0
Branch Conditional to Count Register
PPC440x5 CPU Core User's Manual
LK = 0
LK =1
16 21
as part of the branch condition.
1
Function
bcctr
528 LK
31
Other Registers
Altered
(LR) CIA + 4.
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