Tcr; Figure 10-47. Timer Control Register (Tcr) - IBM PPC440X5 CPU Core User Manual

Preliminary

TCR

SPR 0x154 Supervisor R/W
See Timer Control Register (TCR) on page 215.
WP WIE FP FIE
0 1 2 3 4 5 6 7 8 9 10
WRC DIE

Figure 10-47. Timer Control Register (TCR)

Watchdog Timer Period
00 2
01 2
0:1 WP
10 2
11 2
Watchdog Timer Reset Control
00 No Watchdog Timer reset will occur.
01 Core reset
2:3 WRC
10 Chip reset
11 System reset
Watchdog Timer Interrupt Enable
0 Disable Watchdog Timer interrupt.
4 WIE
1 Enable Watchdog Timer interrupt.
DIE Decrementer Interrupt Enable
0 Disable Decrementer interrupt.
5
1 Enable Decrementer interrupt.
Fixed Interval Timer (FIT) Period
00 2
01 2
6:7 FP
10 2
11 2
FIT Interrupt Enable
0 Disable Fixed Interval Timer interrupt.
8 FIE
1 Enable Fixed Interval Timer interrupt.
Auto-Reload Enable
0 Disable auto reload.
9 ARE
1 Enable auto reload.
10:31 Reserved
regsumm440core.fm.
September 12, 2002
ARE
21
time base clocks
25
time base clocks
29
time base clocks
33
time base clocks
13
time base clocks
17
time base clocks
21
time base clocks
25
time base clocks
PPC440x5 CPU Core User's Manual
TCR[WRC] resets to 0b00.
Type of reset to cause upon Watchdog Timer excep-
tion with TSR[ENW,WIS]=0b11.
This field can be set by software, but cannot be
cleared by software, except by a software-induced
reset.
TCR[ARE] resets to 0b0.
TCR
Timer Control Register
31
Page 515 of 589