Table 10-1. Register Categories - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

Table 10-1. Register Categories

Register Category
Branch Control
Cache Control
Cache Debug
Device Control Implemented outside core
Integer Processing
Interrupt Processing
Processor Control
Storage Control
Page 452 of 589
Register(s)
CR
CTR
LR
DNV0–DNV3
DTV0–DTV3
DVLIM
INV0–INV3
ITV0–ITV3
IVLIM
DCDBTRH, DCDBTRL
ICDBDR, ICDBTRH, ICDBTRL
DAC1–DAC2
DBCR0–DBCR2
DBDR
Debug
DBSR
DVC1–DVC2
IAC1–IAC4
GPR0–GPR31
XER
CSRR0–CSRR1
DEAR
ESR
IVOR0–IVOR15
IVPR
MCSR
MCSRR0-MCSRR1
SRR0–SRR1
CCR0
CCR1
MSR
PIR, PVR
RSTCFG
SPRG0–SPRG3
SPRG4–SPRG7
USPRG0
MMUCR
PID
Model and Access
User
User
User
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor, read-only
Supervisor, read-only
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
User
User
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor
Supervisor, read-only
Supervisor, read-only
Supervisor
User, read-only; Supervisor
User
Supervisor
Supervisor
Preliminary
Type Page
CR 67
SPR 67
SPR 66
SPR 97
SPR 97
SPR 99
SPR 97
SPR 97
SPR 99
SPR 127
SPR 112
SPR 246
SPR 239
SPR 247
SPR 244
SPR 246
SPR 245
DCR 53
GPR 71
SPR 72
SPR 168
SPR 170
SPR 172
SPR 170
SPR 171
SPR 174
SPR 169
SPR 167
SPR 108
SPR 108
MSR 165
SPR 75
SPR 79
SPR 75
SPR 75
SPR 75
SPR 148
SPR 151
regsummIntro.fm.
September 12, 2002