Mcsr; Figure 10-34. Machine Check Status Register (Mcsr) - IBM PPC440X5 CPU Core User Manual

MCSR

Machine Check Status Register
PPC440x5 CPU Core User's Manual
MCSR
SPR 0x23C Supervisor Read/Clear
See Machine Check Status Register (MCSR) on page 174.
DRB
TLBP
MCS DCSP
0 1 2 3 4 5 6 7
IB ICP DCFP
DWB

Figure 10-34. Machine Check Status Register (MCSR)

Machine Check Summary
0 No async machine check exception pending
0 MCS
1 Async machine check exception pending
Instruction PLB Error
0 Exception not caused by Instruction Read PLB
1 IB
1 Exception caused by Instruction Read PLB interrupt
Data Read PLB Error
0 Exception not caused by Data Read PLB interrupt
2 DRB
1 Exception caused by Data Read PLB interrupt
Data Write PLB Error
0 Exception not caused by Data Write PLB interrupt
3 DWB
1 Exception caused by Data Write PLB interrupt
Translation Lookaside Buffer Parity Error
0 Exception not caused by TLB parity error
4 TLBP
1 Exception caused by TLB parity error
Instruction Cache Parity Error
0 Exception not caused by I-cache parity error
5 ICP
1 Exception caused by I-cache parity error
Data Cache Search Parity Error
0 Exception not caused by DCU Search parity error
6 DCSP
1 Exception caused by DCU Search parity error
Data Cache Flush Parity Error
0 Exception not caused by DCU Flush parity error
7 DCFP
1 Exception caused by DCU Flush parity error
Imprecise Machine Check Exception
0 No imprecise machine check exception occurred.
8 IMPE
1 Imprecise machine check exception occurred.
9:31 Reserved
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IMPE
8 9
interrupt request (IRQ)
request (IRQ)
request (IRQ)
request (IRQ)
request (IRQ)
request (IRQ)
Set when a machine check exception occurs
that is handled in the asynchronous fashion.
One of MCSR bits 1:7 will be set simulta-
neously to indicate the exception type. When
MSR[ME] and this bit are both set, Machine
Check interrupt is taken.
Set if and only If the DCU parity error was dis-
covered during a DCU Search operation.
See Data Cache Parity Operations on
page 129.
Set if and only If the DCU parity error was dis-
covered during a DCU Flush operation.
See Data Cache Parity Operations on
page 129.
Set if a machine check exception occurs that
sets MCSR[MCS] (or would if it were not
already set) and MSR[ME] = 0.
regsumm440core.fm.
September 12, 2002
Preliminary
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