Cmpli; Table 9-14. Extended Mnemonics For Cmpli - IBM PPC440X5 CPU Core User Manual

Preliminary

cmpli

Compare Logical Immediate
cmpli BF, 0, RA, IM
10
0 6
4
c 0
0:3
u 16
if (RA) ( 0 || IM) then c
<
16
u
if (RA) ( 0 || IM) then c
>
16
if (RA) ( 0 || IM) then c
=
c XER[SO]
3
n BF
CR[CRn] c
0:3
The IM field is extended to 32 bits by concatenating 16 0-bits to its left. The contents of register RA are
compared with IM using a 32-bit unsigned compare.
The CR field specified by the BF field is updated to reflect the results of the compare and the value of
XER[SO] is placed into the same CR field.
Registers Altered
n ] where n is specified by the BF field
• CR[CR
Invalid Instruction Forms
• Reserved fields
Programming Note
PowerPC Book-E Architecture defines this instruction as cmpli BF,L,RA,IM, where L selects operand size
for 64-bit implementations. For all 32-bit implementations, L = 0 is required (L = 1 is an invalid form); hence
for the PPC440x5 core, use of the extended mnemonic cmplwi BF,RA,IM is recommended.

Table 9-14. Extended Mnemonics for cmpli

Mnemonic Operands
cmplwi
[BF,] RA, IM
instrset.fm.
September 12, 2002
BF RA
9 11
1
0
1
1
1
2
Compare Logical Word Immediate.
Use CR0 if BF is omitted.
Extended mnemonic for
cmpli BF,0,RA,IM
PPC440x5 CPU Core User's Manual
16
Function
cmpli
Compare Logical Immediate
IM
Other Registers
Changed
Page 285 of 589
31