Debug Interrupt - IBM PPC440X5 CPU Core User Manual

Preliminary
When an Instruction TLB Error interrupt occurs, the processor suppresses the execution of the instruction
causing the Instruction TLB Miss exception, the interrupt processing registers are updated as indicated below
(all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR14[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Instruction TLB Error interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.

6.5.16 Debug Interrupt

A Debug interrupt occurs when no higher priority exception exists, a Debug exception exists in the Debug
Status Register (DBSR), the processor is in internal debug mode (DBCR0[IDM]=1), and Debug interrupts are
enabled (MSR[DE] = 1). A Debug exception occurs when a debug event causes a corresponding bit in the
DBSR to be set.
There are several types of Debug exception, as follows:
Instruction Address Compare (IAC) exception
An IAC Debug exception occurs when execution is attempted of an instruction whose
address matches the IAC conditions specified by the various debug facility registers. This
exception can occur regardless of debug mode, and regardless of the value of MSR[DE].
Data Address Compare (DAC) exception
A DAC Debug exception occurs when the DVC mechanism is not enabled, and execution is
attempted of a load, store, icbi, icbt, dcbst, dcbf, dcbz, dcbi, dcbt, or dcbtst instruction
whose target storage operand address matches the DAC conditions specified by the various
debug facility registers. This exception can occur regardless of debug mode, and regardless
of the value of MSR[DE].
Programming Note: The instruction cache management instructions icbi and icbt are
Data Value Compare (DVC) exception
A DVC Debug exception occurs when execution is attempted of a load, store, or dcbz
instruction whose target storage operand address matches the DAC and DVC conditions
intrupts.fm.
September 12, 2002
treated as "loads" from the addressed byte with respect to Debug
exceptions. IAC Debug exceptions are associated with the fetching of
instructions not with the execution of instructions. DAC Debug
exceptions are associated with the execution of instruction cache
management instructions, as well as with the execution of load, store,
and data cache management instructions.
User's Manual
PPC440x5 CPU Core
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