IBM PPC440X5 CPU Core User Manual page 173

Preliminary
Floating Point Operation
0 Exception was not caused by a floating point
instruction.
7 FP
1 Exception was caused by a floating point
instruction.
Store Operation
0 Exception was not caused by a store-type
storage access or cache management
8 ST
instruction.
1 Exception was caused by a store-type storage
access or cache management instruction.
9 Reserved
Data Storage Interrupt—Locking Exception
00 Locking exception did not occur.
10:11 DLK 01 Locking exception was caused by
10 Locking exception was caused by
11 Reserved
AP Operation
0 Exception was not caused by an auxiliary
processor instruction.
12 AP
1 Exception was caused by an auxiliary processor
instruction.
Program Interrupt—Unimplemented Operation
Exception
0 Unimplemented Operation exception did not
13 PUO
occur.
1 Unimplemented Operation exception occurred.
Byte Ordering Exception
0 Byte Ordering exception did not occur.
14 BO
1 Byte Ordering exception occurred.
Program Interrupt—Imprecise Exception
0 Exception occurred precisely; SRR0 contains
the address of the instruction that caused the
exception.
15 PIE
1 Exception occurred imprecisely; SRR0 contains
the address of an instruction after the one which
caused the exception.
16:26 Reserved
Program Interrupt—Condition Register Enable
0 Instruction which caused the exception is not a
floating-point CR-updating instruction.
27 PCRE
1 Instruction which caused the exception is a
floating-point CR-updating instruction.
Program Interrupt—Compare
0 Instruction which caused the exception is not a
floating-point compare type instruction
28 PCMP
1 Instruction which caused the exception is a
floating-point compare type instruction.
intrupts.fm.
September 12, 2002
dcbf
.
icbi
.
This field is only set for a Floating-Point Enabled
exception type Program interrupt, and then only
when the interrupt occurs imprecisely due to
MSR[FE0,FE1] being set to a non-zero value when
an attached floating-point unit is already signaling
the Floating-Point Enabled exception (that is,
FPSCR[FEX] is already 1).
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
This field is only defined for a Floating-Point
Enabled exception type Program interrupt, and
then only when ESR[PIE] is 0.
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
This field is only defined for a Floating-Point
Enabled exception type Program interrupt, and
then only when ESR[PIE] is 0.
User's Manual
PPC440x5 CPU Core
Page 173 of 589