Icbt - IBM PPC440X5 CPU Core User Manual

icbt

Instruction Cache Block Touch
PPC440x5 CPU Core User's Manual
icbt
Instruction Cache Block Touch
icbt RA, RB
31
0 6
EA (RA|0) + (RB)
ICBT(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the instruction block at the EA is not in the instruction cache and the memory page referenced by the EA is
marked as cacheable, the instruction block is fetched into the instruction cache.
If the instruction block at the EA is in the instruction cache, or if the memory page referenced by the EA is
marked as caching inhibited, no operation is performed.
If the memory page referenced by the EA is marked as "no-execute" for the current operating mode (user
mode or supervisor mode, as specified by MSR[PR]), no operation is performed.
This instruction is not allowed to cause Data Storage interrupts nor Data TLB Error interrupts. If execution of
the instruction causes either of these types of exception, then no operation is performed, and no interrupt
occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
This instruction allows a program to begin a cache block fetch from main storage before the program needs
the instruction. The program can later branch to the instruction address and fetch the instruction from the
cache without incurring the latency of a cache miss.
Instruction cache management instructions use MSR[DS], not MSR[IS], as part of the virtual address. Also,
the instruction cache on the PPC440x5 is "virtually-tagged", which means that the EA is converted to a virtual
address (VA), and the VA is compared against the cache tag field. See Instruction Cache Synonyms on
page 107 for more information on the ramifications of virtual tagging on software.
Exceptions
Instruction Storage interrupts and Instruction TLB Error interrupts are associated with exceptions which occur
during instruction fetching, not during instruction execution. Execution of instruction cache management
instructions may cause Data Storage or Data TLB Error exceptions, but are not allowed to cause the associ-
ated interrupt. Instead, if such an exception occurs, then no operation is performed.
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RA RB
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September 12, 2002
Preliminary
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instrset.fm.