Twi - IBM PPC440X5 CPU Core User Manual

Preliminary

twi

Trap Word Immediate
twi TO, RA, IM
3
0 6
if ( ((RA) EXTS(IM)
<
((RA) EXTS(IM)
>
((RA) EXTS(IM)
=
u
((RA) EXTS(IM)
<
u
((RA) EXTS(IM)
>
SRR0 address of twi instruction
SRR1 MSR
ESR[PTR] 1 (other bits cleared)
MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS])
PC IVPR || IVOR6
0:15
else no operation
Register RA is compared with the sign-extended IM field. If any comparison condition selected by the TO field
is true, a Trap exception type Program interrupt occurs as follows (see Program Interrupt on page 187 for
more information on Program interrupts). The contents of the MSR are copied into SRR1 and the address of
twi instruction) is placed into SRR0. ESR[PTR] is set to 1 and the other bits ESR bits cleared to indicate
the
the type of exception causing the Program interrupt.
The program counter (PC) is then loaded with the interrupt vector address. The interrupt vector address is
formed by concatenating the high halfword of the Interrupt Vector Prefix Register (IVPR), bits 16:27 of the
Interrupt Vector Offset Register 6 (IVOR6), and 0b0000.
MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] are set to 0.
Program execution continues at the new address in the PC.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• SRR0 (if trap condition is met)
• SRR1 (if trap condition is met)
• MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] (if trap condition is met)
• ESR (if trap condition is met)
Invalid Instruction Forms
• Reserved fields
Programming Notes
This instruction can be inserted into the execution stream by a debugger to implement breakpoints, and is not
typically used by application code.
instrset.fm.
September 12, 2002
TO RA
11
TO = 1)
0
TO = 1)
1
TO = 1)
2
TO = 1)
3
TO = 1) )
4
4
|| 0
16:27
PPC440x5 CPU Core User's Manual
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0
Trap Word Immediate
IM
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twi
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