IBM PPC440X5 CPU Core User Manual page 551

Preliminary
Table A-1. PPC440x5 Instruction Syntax Summary (continued)
Mnemonic Operands
sthu
RS, D(RA)
sthux
RS, RA, RB
sthx
RS, RA, RB
stmw
RS, D(RA)
stswi
RS, RA, NB
stswx
RS, RA, RB
stw
RS, D(RA)
stwbrx
RS, RA, RB
stwcx.
RS, RA, RB
stwu
RS, D(RA)
stwux
RS, RA, RB
stwx
RS, RA, RB
instalfa.fm.
September 12, 2002
Function
Store halfword (RS) 16:31 in memory at
EA = (RA|0) + EXTS(D).
Update the base address,
(RA) EA.
Store halfword (RS) 16:31 in memory at
EA = (RA|0) + (RB).
Update the base address,
(RA) EA.
Store halfword (RS) 16:31 in memory at
EA = (RA|0) + (RB).
Store consecutive words from RS through GPR(31) in memory
starting at
EA = (RA|0) + EXTS(D).
Store consecutive bytes in memory starting at EA=(RA|0).
Number of bytes n=32 if NB=0, else n=NB.
Bytes are unstacked from CEIL(n/4)
consecutive registers starting with RS.
GPR(0) is consecutive to GPR(31).
Store consecutive bytes in memory starting at EA=(RA|0)+(RB).
Number of bytes n=XER[TBC].
Bytes are unstacked from CEIL(n/4)
consecutive registers starting with RS.
GPR(0) is consecutive to GPR(31).
Store word (RS) in memory at
EA = (RA|0) + EXTS(D).
Store word (RS) byte-reversed in memory at EA = (RA|0) +
(RB).
(RS)
MS(EA, 4)
24:31
(RS)
(RS) 8:15
0:7
Store word (RS) in memory at EA = (RA|0) + (RB)
only if reservation bit is set.
if RESERVE = 1 then
(RS)
MS(EA, 4)
RESERVE 0
2
1
(CR[CR0]) 0
else
2
0
(CR[CR0]) 0
Store word (RS) in memory at
EA = (RA|0) + EXTS(D).
Update the base address,
(RA) EA.
Store word (RS) in memory at
EA = (RA|0) + (RB).
Update the base address,
(RA) EA.
Store word (RS) in memory at
EA = (RA|0) + (RB).
(RS)
16:23
XER
so
XER
so.
User's Manual
PPC440x5 CPU Core
Other Registers
Page
Changed
415
416
417
418
418
421
422
423
424
426
427
428
Page 551 of 589