IBM PPC440X5 CPU Core User Manual page 573

Preliminary
,
btctrl 277
,
btl 274
,
btla 274
,
btlr 281
,
btlrl 281
,
bun 274
,
buna 274
,
bunctr 277
,
bunctrl 277
,
bunl 274
,
bunla 274
,
bunlr 281
,
bunlrl 281
,
byte ordering 42
,
big endian, defined 43
, ,
instructions 44 45
,
little endian, defined 43
structure mapping
,
big-endian mapping
little endian mapping
C
,
cache block, defined 108
cache line
See also cache block
,
cache line locking 99
cache line replacement policy
cache locking transient mechanism
cache management instructions
summary
,
data cache 125
,
instruction cache 108
,
caching inhibited 145
, , , ,
CCR0 76 108 110 126
,
CCR1 462
change status management
,
clrlslwi 400
,
clrlslwi. 400
,
clrlwi 400
,
clrlwi. 400
,
clrrwi 401
,
clrrwi. 401
,
cmp 282
,
cmpi 283
,
cmpl 284
,
cmpli 285
,
cmplw 284
,
cmplwi 285
,
cmpw 282
,
cmpwi 283
,
cntlzw 286
,
cntlzw. 286
code
,
self-modifying 106
ppc440x5IX.fm.
September 12, 2002
43
,
44
,
96
,
99
,
460
,
154
coherence
,
data cache 124
coherency
,
instruction cache 106
compare
,
arithmetic 71
,
logical 71
Condition Register. See also CR
,
context synchronization 82
control
,
data cache 125
,
instruction cache 108
conventions
,
notational 24
, ,
CR 67 464
defined
,
CR updating instructions
instructions
integer
,
CR 70
,
crand 287
,
crandc 288
,
crclr 294
,
creqv 289
,
Critical Input interrupt 178
,
critical interrupts 161
Critical Save/Restore Register 0
Critical Save/Restore Register 1
,
crmove 292
,
crnand 290
,
crnor 291
,
crnot 291
,
cror 292
,
crorc 293
,
crset 289
,
crxor 294
, , ,
CSRR0 168 169 465
, , ,
CSRR1 168 169 466
, ,
CTR 67 467
D
DAC
debug events
applied to instructions that result in multiple storage
accesses
applied to various instruction types
,
fields 226
,
overview 226
,
processing 229
registers
,
DAC1–DAC2 246
, ,
DAC1–DAC2 246 468
Data Address Compare Register (DAC1)
data address compare See also DAC
User's Manual
PPC440x5 CPU Core
69
, ,
168 169
, ,
168 169
,
230
,
230
,
246
,
226
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