Stwcx - IBM PPC440X5 CPU Core User Manual

stwcx.

Store Word Conditional Indexed
PPC440x5 CPU Core User's Manual
stwcx.
Store Word Conditional Indexed
stwcx. RS, RA, RB
31
0 6
EA (RA|0) + (RB)
if RESERVE = 1 then
MS(EA, 4) (RS)
RESERVE 0
2
(CR[CR0]) 0
else
2
(CR[CR0]) 0
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
If the reservation bit contains 1 when the instruction is executed, the contents of register RS are stored into
the word at the EA and the reservation bit is cleared. If the reservation bit contains 0 when the instruction is
executed, no store operation is performed.
CR[CR0] is set as follows:
• CR[CR0] are cleared
0:1
• CR[CR0] is set to indicate whether or not the store was performed (1 indicates that it was)
2
• CR[CR0] is set to the contents of the XER[SO] bit
3
Registers Altered
• CR[CR0]
Programming Notes
The lwarx and stwcx. instructions are typically paired in a loop, as shown in the following example, to create
the effect of an atomic operation to a memory area used as a semaphore between multiple processes. Only
lwarx can set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its completion, whether or not
stwcx. actually stored (RS) to memory. CR[CR0]
memory.
loop: lwarx # read the semaphore from memory; set reservation
"alter" # change the semaphore bits in the register as required
stwcx. # attempt to store the semaphore; reset reservation
bne loop # some other process intervened and cleared the reservation prior to the above
# stwcx.; try again
The PowerPC Book-E architecture specifies that the EA for the lwarx instruction must be word-aligned (that
is, a multiple of 4 bytes); otherwise, the result is undefined. Although the PPC440x5 will execute stwcx.
regardless of the EA alignment, in order for the operation of the pairing of lwarx and stwcx. to produce the
desired result, software must ensure that the EA for both instructions is word-aligned. This requirement is due
to the manner in which misaligned storage accesses may be broken up into separate, aligned accesses by
the PPC440x5.
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RS RA
11
1 XER[SO]
0 XER[SO]
RB
16 21
must be examined to determine whether (RS) was sent to
2
Preliminary
150 1
31
instrset.fm.
September 12, 2002