Pseudocode - IBM PPC440X5 CPU Core User Manual

Preliminary
These instruction fields contain values, such as opcodes, that cannot be altered. The instruction format
diagrams specify the values of defined fields.
• Variable
These fields contain operands, such as general purpose register specifiers and immediate values, each
of which may contain any one of a number of values. The instruction format diagrams specify the field
names of variable fields.
• Reserved
Bits in a reserved field should be set to 0. In the instruction format diagrams, reserved fields are shaded.
If any bit in a defined field does not contain the specified value, the instruction is illegal and an Illegal Instruc-
tion exception type Program interrupt occurs. If any bit in a reserved field does not contain 0, the instruction
form is invalid and its result is architecturally undefined. Unless otherwise noted, the PPC440x5 core will
execute all invalid instruction forms without causing an Illegal Instruction exception.

9.3 Pseudocode

The pseudocode that appears in the instruction descriptions provides a semi-formal language for describing
instruction operations.
The pseudocode uses the following notation:
+
%
u u
,
< >
(GPR(r))
(RA|0)
(Rx)
0bn
0xn
<, >
=
CEIL(x)
CIA
DCR(DCRN)
instrset.fm.
September 12, 2002
Twos complement addition
Remainder of an integer division; (33 % 32) = 1.
Unsigned comparison relations
The contents of GPR r, where 0
The contents of the register RA or 0, if the RA field is 0.
The contents of a GPR, where
A binary number
A hexadecimal number
Signed comparison relations
Assignment
Equal, not equal relations
Least integer x.
Current instruction address; the 32-bit address of the instruction being
described by a sequence of pseudocode. This address is used to set the
next instruction address (NIA). Does not correspond to any architected
register.
A Device Control Register (DCR) specified by the DCRF field in an
mfdcr or mtdcr instruction
PPC440x5 CPU Core User's Manual
r 31.
is A, B, S, or T
x
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