Icdbtrh; Figure 10-26. Instruction Cache Debug Tag Register High (Icdbtrh) - IBM PPC440X5 CPU Core User Manual

ICDBTRH

Instruction Cache Debug Tag Register High
PPC440x5 CPU Core User's Manual
ICDBTRH
SPR 0x39F Supervisor Read-Only
See icread Operation on page 112.
0

Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH)

0:23 Tag Effective Address
Cache Line Valid
0 Cache line is not valid.
24 V
1 Cache line is valid.
25:26 TPAR Tag Parity
27 DAPAR Instruction Data parity
28:31 Reserved
Page 492 of 589
TEA
TPAR
23 24 25 26 27 28
DAPAR
V
Bits 0:23 of the 32-bit effective address associated
with the cache line read by icread.
The valid indicator for the cache line read by
icread.
The parity bits for the address tag for the cache
line read by icread, if CCR0[CRPE] is set.
The parity bit for the instruction word at the 32-bit
effective address specified in the icread instruc-
tion, if CCR0[CRPE] is set.
Preliminary
31
regsumm440core.fm.
September 12, 2002