IBM PPC440X5 CPU Core User Manual page 488

ESR (cont.)
Exception Syndrome Register
PPC440x5 CPU Core User's Manual
Byte Ordering Exception
0 Byte Ordering exception did not occur.
14 BO
1 Byte Ordering exception occurred.
Program Interrupt—Imprecise Exception
0 Exception occurred precisely; SRR0 contains
the address of the instruction that caused the
exception.
15 PIE
1 Exception occurred imprecisely; SRR0 contains
the address of an instruction after the one which
caused the exception.
16:26 Reserved
Program Interrupt—Condition Register Enable
0 Instruction which caused the exception is not a
floating-point CR-updating instruction.
27 PCRE
1 Instruction which caused the exception is a
floating-point CR-updating instruction.
Program Interrupt—Compare
0 Instruction which caused the exception is not a
floating-point compare type instruction
28 PCMP
1 Instruction which caused the exception is a
floating-point compare type instruction.
Program Interrupt—Condition Register Field
If ESR[PCRE]=1, this field indicates which CR field
29:31 PCRF
was to be updated by the floating-point instruction
which caused the exception.
Page 488 of 589
This field is only set for a Floating-Point Enabled
exception type Program interrupt, and then only
when the interrupt occurs imprecisely due to
MSR[FE0,FE1] being set to a non-zero value when
an attached floating-point unit is already signaling
the Floating-Point Enabled exception (that is,
FPSCR[FEX] is already 1).
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
This field is only defined for a Floating-Point
Enabled exception type Program interrupt, and
then only when ESR[PIE] is 0.
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
This field is only defined for a Floating-Point
Enabled exception type Program interrupt, and
then only when ESR[PIE] is 0.
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
This field is only defined for a Floating-Point
Enabled exception type Program interrupt, and
then only when ESR[PIE] is 0.
Preliminary
regsumm440core.fm.
September 12, 2002