Store Operations - IBM PPC440X5 CPU Core User Manual

Preliminary

4.3.1.3 Store Operations

The processing of store instructions in the DCC is affected by several factors, including the caching inhibited
(I), write-through (W), and guarded (G) storage attributes, as well as whether or not the allocation of data
cache lines is enabled for cacheable store misses. There are three different behaviors to consider:
• Whether a data cache line is allocated (if the line is not already in the data cache)
• Whether the data is written directly to memory or only into the data cache
• Whether the store data can be gathered with store data from previous or subsequent store instructions
before being written to memory
Allocation of Data Cache Line on Store Miss
Of course, if the caching inhibited attribute is set for the memory page being referenced by the store instruc-
tion, no data cache line will be allocated. For cacheable store accesses, allocation is controlled by one of two
mechanisms: either by a "global" control bit in the Memory Management Unit Control Register (MMUCR),
which is applied to all cacheable store accesses regardless of address; or by the U2 storage attribute for the
memory page being accessed. See Memory Management Unit Control Register (MMUCR) on page 148 for
more information on how store miss cache line allocation is controlled.
Regardless of which mechanism is controlling the allocation, if the corresponding bit is set, the cacheable
store miss is handled as a store without allocate (SWOA). That is, if SWOA is indicated, then if the access
misses in the data cache, then the line will not be allocated (read from memory), and instead the byte[s] being
stored will be written directly to memory. Of course, if the cache line has already been allocated and is being
read into a DCLFD buffer (due perhaps to a previous cacheable load access), then the SWOA indication is
ignored and the access is treated as if it were a store with allocate. Similarly, if SWOA is not indicated, the
cache line will be allocated and the cacheable store miss will result in the cache line being read from memory.
Direct Write to Memory
Of course, if the caching inhibited attribute is set for the memory page being referenced by the store instruc-
tion, the data must be written directly to memory. For cacheable store accesses that are also write-through,
the store data will also be written directly to memory, regardless of whether the access hits in the data cache,
and independent of the SWOA mechanism. For cacheable store accesses that are not write through, whether
the data is written directly to memory depends on both whether the access hits or misses in the data cache,
and the SWOA mechanism. If the access is either a hit in the data cache, or if SWOA is not indicated, then
the data will only be written to the data cache, and not to memory. Conversely, if the cacheable store access
is both a miss in the data cache and SWOA is indicated, the access will be treated as if it were caching inhib-
ited and the data will be written directly to memory and not to the data cache (since the data cache line is
neither there already nor will it be allocated).
Store Gathering
In general, memory write operations caused by separate store instructions that specify locations in either
write-through or caching inhibited storage may be gathered into one simultaneous access to memory. Simi-
larly, store accesses that are handled as if they were caching inhibited (due to their being both a miss in the
data cache and being indicated as SWOA) may be gathered. Store accesses that are only written into the
data cache do not need to be gathered, because there is no performance penalty associated with the sepa-
rate accesses to the array.
cache.fm.
September 12, 2002
User's Manual
PPC440x5 CPU Core
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