Core Configuration Register 1 (Ccr1); Figure 4-6. Core Configuration Register 1 (Ccr1) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
Force Load/Store Alignment
0 No Alignment exception on integer
23 FLSTA
1 An alignment exception occurs on
24:27 Reserved
28:29 ICSLC Instruction Cache Speculative Line Count
30:31 ICSLT Instruction Cache Speculative Line Threshold
4.2.4.3 Core Configuration Register 1 (CCR1)
The CCR1 register controls parity error insertion for software testing, one option for line flush behavior in the
D-cache, and a control bit that selects the timer input clock. Each of the these functions is discussed in more
detail in the related sections of this manual.
Figure 4-6 illustrates the fields of the CCR1 register.
ICDPEI
0
Figure 4-6. Core Configuration Register 1 (CCR1)
Instruction Cache Data Parity Error Insert
0 record even parity (normal)
0:7 ICDPEI
1 record odd parity (simulate parity error)
Instruction Cache Tag Parity Error Insert
0 record even parity (normal)
8:9 ICTPEI
1 record odd parity (simulate parity error)
Data Cache Tag Parity Error Insert
0 record even parity (normal)
10:11 DCTPEI
1 record odd parity (simulate parity error)
Data Cache Data Parity Error Insert
0 record even parity (normal)
12 DCDPEI
1 record odd parity (simulate parity error)
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storage access instructions, regardless
of alignment
integer storage access instructions if
data address is not on an operand
boundary.
DCTPEI DCUPEI FCOM
7 8 9 10 11 12 13 14 15 16
ICTPEI DCDPEI DCMPEI
See Load and Store Alignment on page 117.
Number of additional lines (0–3) to fill on instruc-
tion fetch miss.
See Speculative Prefetch Mechanism on
page 105.
Number of doublewords that must have already
been filled in order that the current speculative
not
line fill is abandoned on a redirection of the
instruction stream.
See Speculative Prefetch Mechanism on
page 105.
FFF
19 20 21 23 24 25
MMUPEI TCS
Controls inversion of parity bits recorded when the
instruction cache is filled. Each of the 8 bits corre-
sponds to one of the instruction words in the line.
Controls inversion of parity bits recorded for the tag
field in the instruction cache.
Controls inversion of parity bits recorded for the tag
field in the data cache.
Controls inversion of parity bits recorded for the
data field in the data cache.
Preliminary
31
cache.fm.
September 12, 2002