Figure 2-11. Core Configuration Register 0 (Ccr0) - IBM PPC440X5 CPU Core User Manual

Preliminary
PRE
0 1 2 3 4 5
CRPE
Figure 2-11. Core Configuration Register 0 (CCR0)
0 Reserved
Parity Recoverability Enable
0 Semi-recoverable parity mode enabled
1 PRE
1 Fully recoverable parity mode enabled
2:3 Reserved
Cache Read Parity Enable
0 Disable parity information reads
4 CRPE
1 Enable parity information reads
5:9 Reserved
Disable Store Gathering
0 Enabled; stores to contiguous addresses
10 DSTG
1 Disabled; all stores to memory will be
Disable APU Instruction Broadcast
0 Enabled.
11 DAPUIB
1 Disabled; instructions not broadcast to
12:15 Reserved
Disable Trace Broadcast
0 Enabled.
16 DTB
1 Disabled; no trace information is
Guaranteed Instruction Cache Block Touch
0 icbt may be abandoned without having
17 GICBT
1 icbt is guaranteed to fill cache line even
Guaranteed Data Cache Block Touch
0 dcbt/dcbtst may be abandoned without
18 GDCBT
1 dcbt/dcbtst are guaranteed to fill cache
19:22 Reserved
prgmodel.fm.
September 12, 2002
DSTG
9 10 11 12
DAPUIB
for data cache
for data cache
may be gathered into a single transfer
performed independently
APU for decoding
broadcast.
filled cache line if instruction pipeline
stalls.
if instruction pipeline stalls.
having filled cache line if load/store
pipeline stalls.
line even if load/store pipeline stalls.
DTB GDCBT
15 16 17 18 19 22 23 24
GICBT
Must be set to 1 to guarantee full recoverability
from MMU and data cache parity errors.
When enabled, execution of icread, dcread, or
tlbre loads parity information into the ICDBTRH,
DCDBTRL, or target GPR, respectively.
See Store Gathering on page 119.
This mechanism is provided as a means of reduc-
ing power consumption when an auxilliary pro-
cessor is not attached and/or is not being used.
See Initialization on page 85.
This mechanism is provided as a means of reduc-
ing power consumption when instruction tracing is
not needed.
See Initialization on page 85.
See icbt Operation on page 111.
See Data Cache Control and Debug on
page 125.
User's Manual
PPC440x5 CPU Core
ICSLC
27 28 29 30 31
FLSTA
Page 77 of 589
ICSLT