IBM PPC440X5 CPU Core User Manual page 157

Preliminary
tlbwe Rs,Ra,2
isync
mtspr CCR1, Rz
isync
tlbre RT,RA,WS
mmu.fm.
September 12, 2002
; write some data to the TLB with bad parity
; wait for the tlbwe(s) to finish
; Reset CCR1[MMUPEI]
; wait for the CCR1 context to update
; tlbre with bad parity causes interrupt
User's Manual
PPC440x5 CPU Core
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