Reading The Time Base; Writing The Time Base; Figure 7-2. Time Base Lower (Tbl); Figure 7-3. Time Base Upper (Tbu) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
Software access to TBU and TBL is non-privileged for read but privileged for write, and hence different SPR
numbers are used for reading than for writing. TBU and TBL are written using
The period of the 64-bit time base is approximately 1462 years for a 400 MHz clock source. The time base
value itself does not generate any exceptions, even when it wraps. For most applications, the time base is set
once at system reset and only read thereafter. Note that Fixed Interval Timer and Watchdog Timer excep-
tions (discussed below) are caused by 0 1 transitions of selected bits from the time base. Transitions of
these bits caused by software alteration of the time base have the same effect as transitions caused by
normal incrementing of the time base.
Figure 7-2 illustrates the TBL.
0

Figure 7-2. Time Base Lower (TBL)

0:31 Time Base Lower
Figure 7-3 illustrates the TBU.
0

Figure 7-3. Time Base Upper (TBU)

0:31 Time Base Upper

7.1.1 Reading the Time Base

The following code provides an example of reading the time base.
loop:
mfspr Rx,TBU
mfspr Ry,TBL
mfspr Rz,TBU
cmpw Rz, Rx
bne loop
The comparison and loop ensure that a consistent pair of values is obtained.

7.1.2 Writing the Time Base

The following code provides an example of writing the time base.
lwz Rx, upper
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# read TBU into GPR Rx
# read TBL into GPR Ry
# read TBU again, this time into GPR Rz
# see if old = new
# loop/reread if rollover occurred
# load 64-bit time base value into GPRs Rx and Ry
mtspr and read using mfspr .
Low-order 32 bits of time base.
High-order 32 bits of time base.
Preliminary
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timers.fm.
September 12, 2002