Dbcr1; Figure 10-9. Debug Control Register 1 (Dbcr1) - IBM PPC440X5 CPU Core User Manual

Preliminary

DBCR1

SPR 0x135 Supervisor R/W
See Debug Control Register 1 (DBCR1) on page 240.
IAC1US IAC2US
0 1 2 3 4 5 6 7 8 9 10
IAC1ER
IAC2ER

Figure 10-9. Debug Control Register 1 (DBCR1)

Instruction Address Compare (IAC) 1 User/Super-
visor
00 Both
0:1 IAC1US
01 Reserved
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 1 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
2:3 IAC1ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 2 User/Supervisor
00 Both
01 Reserved
4:5 IAC2US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 2 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
6:7 IAC2ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 1/2 Mode
00 Exact match
8:9 IAC12M
01 Reserved
10 Range inclusive
11 Range exclusive
10:14 Reserved
IAC 1/2 Auto-Toggle Enable
0 Disable IAC 1/2 auto-toggle
15 IAC12AT
1 Enable IAC 1/2 auto-toggle
IAC 3 User/Supervisor
00 Both
01 Reserved
16:17 IAC3US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 3 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
18:19 IAC3ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
regsumm440core.fm.
September 12, 2002
IAC12M
14 15 16 17 18 19 20 21 22 23 24 25 26
IAC12AT
PPC440x5 CPU Core User's Manual
IAC4US
IAC3US
IAC3ER
IAC4ER
Match if address[0:29] = IAC 1/2[0:29]; two inde-
pendent compares
Match if IAC1
Match if address < IAC1 OR address
DBCR1
Debug Control Register 1
IAC34M
30 31
IAC34AT
address < IAC2
IAC2
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