Memory Coherence Required (M); Guarded (G); Endian (E) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core Preliminary
See Instruction and Data Caches on page 95 for more information on the handling of accesses to caching
inhibited storage.

5.6.3 Memory Coherence Required (M)

The memory coherence required (M) storage attribute is defined by the architecture to support cache and
memory coherency within multiprocessor shared memory systems. Because the PPC440x5 does not provide
hardware support for multiprocessor coherence, the memory coherence required storage attribute has no
effect. If a TLB entry is created with M = 1, any storage accesses to the page associated with that TLB entry
are indicated, using the corresponding transfer attribute interface signal, as being memory coherence
required, but the setting has no effect on the operation within the PPC440x5 core.

5.6.4 Guarded (G)

The guarded storage attribute is provided to control "speculative" access to "non-well-behaved" memory loca-
tions. Storage is said to be "well-behaved" if the corresponding real storage exists and is not defective, and if
the effects of a single access to it are indistinguishable from the effects of multiple identical accesses to it. As
such, data and instructions can be fetched out-of-order from well-behaved storage without causing undesired
side effects.
In general, storage that is not well-behaved should be marked as guarded. Because such storage may repre-
sent a control register on an I/O device or may include locations that do not exist, an out-of-order access to
such storage may cause an I/O device to perform unintended operations or may result in a Machine Check
exception. For example, if the input buffer of a serial I/O device is memory-mapped, then an out-of-order or
speculative access to that location could result in the loss of an item of data from the input buffer, if the
instruction execution is interrupted and later re-attempted.
A data access to a guarded storage location is performed only if either the access is caused by an instruction
that is known to be required by the sequential execution model, or the access is a load and the storage loca-
tion is already in the data cache. Once a guarded data storage access is initiated, if the storage is also
caching inhibited then only the bytes specifically requested are accessed in memory, according to the
operand size for the instruction type. Data storage accesses to guarded storage which is marked as cache-
able may access the entire cache block, either in the cache itself or in memory.
Instruction fetch is not affected by guarded storage. While the architecture does not prohibit instruction
fetching from guarded storage, system software should generally prevent such instruction fetching by
marking all guarded pages as "no-execute" (UX/SX = 0). Then, if an instruction fetch is attempted from such
a page, the memory access will not occur and an Execute Access Control exception type Instruction Storage
interrupt will result if and when execution is attempted for an instruction at any address within the page.
See Section 4 Instruction and Data Caches on page 95 for more information on the handling of accesses to
guarded storage. Also see Partially Executed Instructions on page 164 for information on the relationship
between the guarded storage attribute and instruction restart and partially executed instructions.

5.6.5 Endian (E)

The endian (E) storage attribute controls the byte ordering with which load, store, and fetch operations are
performed. Byte ordering refers to the order in which the individual bytes of a multiple-byte scalar operand are
arranged in memory. The operands in a memory page with E=0 are arranged with big-endian byte ordering,
mmu.fm.
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