Integer Instructions; Integer Storage Access Instructions; Table 2-4. Instruction Categories - IBM PPC440X5 CPU Core User Manual

Preliminary
Table 2-4 summarizes the PPC440x5 instruction set by category. Instructions within each category are
described in subsequent sections.

Table 2-4. Instruction Categories

Category
Integer Storage Access
Integer Arithmetic
Integer Logical
Integer Compare
Integer
Integer Select
Integer Trap
Integer Rotate
Integer Shift
Branch
Condition Register Logical
Register Management
Processor Control
System Linkage
Processor Synchronization
Cache Management
Storage Control
TLB Management
Storage Synchronization
Allocated Arithmetic
Allocated Logical
Allocated
Allocated Cache Management
Allocated Cache Debug

2.4.1 Integer Instructions

Integer instructions transfer data between memory and the GPRs, and perform various operations on the
GPRs. This category of instructions is further divided into seven sub-categories, described below.

2.4.1.1 Integer Storage Access Instructions

Integer storage access instructions load and store data between memory and the GPRs. These instructions
operate on bytes, halfwords, and words. Integer storage access instructions also support loading and storing
multiple registers, character strings, and byte-reversed data, and loading data with sign-extension.
Table 2-5 shows the integer storage access instructions in the PPC440x5. In the table, the syntax "[
cates that the instruction has both an "update" form (in which the RA addressing register is updated with the
calculated address) and a "non-update" form. Similarly, the syntax "[
prgmodel.fm.
September 12, 2002
Subcategory
load, store
add, subtract, multiply, divide, negate
and, andc, or, orc, xor, nand, nor, xnor, extend sign, count
leading zeros
compare, compare logical
select operand
trap
rotate and insert, rotate and mask
shift left, shift right, shift right algebraic
branch, branch conditional, branch to link, branch to count
crand, crandc, cror, crorc, crnand, crnor, crxor, crxnor
move to/from SPR, move to/from DCR, move to/from MSR,
write to external interrupt enable bit, move to/from CR
system call, return from interrupt, return from critical interrupt,
return from machine check interrupt
instruction synchronize
data allocate, data invalidate, data touch, data zero, data flush,
data store, instruction invalidate, instruction touch
read, write, search, synchronize
memory synchronize, memory barrier
multiply-accumulate, negative multiply-accumulate, multiply
halfword
detect left-most zero byte
data congruence-class invalidate, instruction congruence-class
invalidate
data read, instruction read
PPC440x5 CPU Core
Instruction Types
x ]" indicates that the instruction has both
User's Manual
u ]" indi-
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