Esr; Figure 10-22. Exception Syndrome Register (Esr) - IBM PPC440X5 CPU Core User Manual

Preliminary

ESR

SPR 0x03E Supervisor R/W
See Exception Syndrome Register (ESR) on page 172.
MCI PIL PTR
0 1 3 4 5 6
PPR

Figure 10-22. Exception Syndrome Register (ESR)

Machine Check—Instruction Fetch Exception
0 Instruction Machine Check exception did not
0 MCI
occur.
1 Instruction Machine Check exception occurred.
1:3 Reserved
Program Interrupt—Illegal Instruction Exception
0 Illegal Instruction exception did not occur.
4 PIL
1 Illegal Instruction exception occurred.
Program Interrupt—Privileged Instruction Excep-
tion
5 PPR
0 Privileged Instruction exception did not occur.
1 Privileged Instruction exception occurred.
Program Interrupt—Trap Exception
0 Trap exception did not occur.
6 PTR
1 Trap exception occurred.
Floating Point Operation
0 Exception was not caused by a floating point
instruction.
7 FP
1 Exception was caused by a floating point
instruction.
Store Operation
0 Exception was not caused by a store-type
storage access or cache management
8 ST
instruction.
1 Exception was caused by a store-type storage
access or cache management instruction.
9 Reserved
Data Storage Interrupt—Locking Exception
00 Locking exception did not occur.
01 Locking exception was caused by dcbf.
10:11 DLK
10 Locking exception was caused by
11 Reserved
AP Operation
0 Exception was not caused by an auxiliary
processor instruction.
12 AP
1 Exception was caused by an auxiliary processor
instruction.
Program Interrupt—Unimplemented Operation
Exception
0 Unimplemented Operation exception did not
13 PUO
occur.
1 Unimplemented Operation exception occurred.
regsumm440core.fm.
September 12, 2002
ST BO
AP
7 8 9 10 11 12 13 14 15 16
FP DLK PUO
PPC440x5 CPU Core User's Manual
PIE
This is an implementation-dependent field of the
ESR and is not part of the PowerPC Book-E Archi-
tecture.
icbi
.
ESR
Exception Syndrome Register
PCRE PCRF
26 27 28 29 31
PCMP
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