Dcdbtrl; Figure 10-14. Data Cache Debug Tag Register Low (Dcdbtrl) - IBM PPC440X5 CPU Core User Manual

Preliminary

DCDBTRL

SPR 0x39C Supervisor Read-Only
See dcread Operation on page 127.
0

Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL)

0:12 Reserved
13 UPAR U bit parity
14:15 TPAR Tag parity
16:19 DPAR Data parity
20:23 MPAR Modified (dirty) parity
24:27 D Dirty Indicators
28 U0 U0 Storage Attribute
29 U1 U1 Storage Attribute
30 U2 U2 Storage Attribute
31 U3 U3 Storage Attribute
regsumm440core.fm.
September 12, 2002
DPAR
UPAR
12 13 14 15 16 19 20
TPAR
Data Cache Debug Tag Register Low
PPC440x5 CPU Core User's Manual
D
23 24
MPAR
The parity for the U0-U3 bits in the cache line read
by dcread if CCR0[CRPE] = 1, otherwise 0.
The parity for the tag bits in the cache line read by
dcread if CCR0[CRPE] = 1, otherwise 0.
The parity check values for the data bytes in the
word read by dcread if CCR0[CRPE] = 1, other-
wise 0.
The parity for the modified (dirty) indicators for
each of the four doublewords in the cache line read
by dcread if CCR0[CRPE] = 1, otherwise 0.
The "dirty" (modified) indicators for each of the four
doublewords in the cache line read by dcread.
The U0 storage attribute for the memory page
associated with this cache line read by dcread.
The U1 storage attribute for the memory page
associated with this cache line read by dcread.
The U2 storage attribute for the memory page
associated with this cache line read by dcread.
The U3 storage attribute for the memory page
associated with this cache line read by dcread.
DCDBTRL
U1
U3
27 28 29 30 31
U0 U2
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