Dbcr0; Figure 10-8. Debug Control Register 0 (Dbcr0) - IBM PPC440X5 CPU Core User Manual

Preliminary

DBCR0

SPR 0x134 Supervisor R/W
See Debug Control Register 0 (DBCR0) on page 239.
EDM RST BRT TRAP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IDM ICMP IRPT

Figure 10-8. Debug Control Register 0 (DBCR0)

External Debug Mode
0 Disable external debug mode.
0 EDM
1 Enable external debug mode.
Internal Debug Mode
1 IDM 0 Disable internal debug mode.
1 Enable internal debug mode.
Reset
00 No action
01 Core reset
2:3 RST
10 Chip reset
11 System reset
Attention: Writing 01, 10, or 11 to this field causes a processor reset to occur.
Instruction Completion Debug Event
4 ICMP 0 Disable instruction completion debug event.
1 Enable instruction completion debug event.
Branch Taken Debug Event
0 Disable branch taken debug event.
5 BRT
1 Enable branch taken debug event.
Interrupt Debug Event
0 Disable interrupt debug event.
6 IRPT
1 Enable interrupt debug event.
Trap Debug Event
0 Disable trap debug event.
7 TRAP
1 Enable trap debug event.
Instruction Address Compare (IAC) 1 Debug Event
0 Disable IAC 1 debug event.
8 IAC1
1 Enable IAC 1 debug event.
IAC 2 Debug Event
0 Disable IAC 2 debug event.
9 IAC2
1 Enable IAC 2 debug event.
IAC 3 Debug Event
10 IAC3 0 Disable IAC 3 debug event.
1 Enable IAC 3 debug event.
IAC 4 Debug Event
0 Disable IAC 4 debug event.
11 IAC4
1 Enable IAC 4 debug event.
regsumm440core.fm.
September 12, 2002
IAC2 IAC4 DAC1W DAC2W
IAC1 IAC3 DAC1R DAC2R
PPC440x5 CPU Core User's Manual
RET
Instruction completions do not cause
instruction completion debug events if
MSR[DE] = 0 in internal debug mode,
unless also in external debug mode or
debug wait mode.
Taken branches do not cause branch
taken debug events if MSR[DE] = 0 in
internal debug mode, unless also in
external debug mode or debug wait
mode.
Critical interrupts do not cause interrupt
debug events in internal debug mode,
unless also in external debug mode or
debug wait mode.
DBCR0
Debug Control Register 0
FT
30 31
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