Addis; Table 9-7. Extended Mnemonics For Addis - IBM PPC440X5 CPU Core User Manual

Preliminary

addis

Add Immediate Shifted
addis RT, RA, IM
15
0 6
(RT) (RA|0) + (IM
If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT.
If the RA field is nonzero, the contents of register RA are added to the contents of the extended IM field. The
sum is stored into register RT.
Registers Altered
• RT
Programming Note
An addi instruction stores a sign-extended 16-bit value in a GPR. An addis instruction followed by an ori
instruction stores an arbitrary 32-bit value in a GPR, as shown in the following example:
addis RT, 0, high 16 bits of value
ori RT, RT, low 16 bits of value

Table 9-7. Extended Mnemonics for addis

Mnemonic Operands
lis
RT, IM
subis
RT, RA, IM
instrset.fm.
September 12, 2002
RT RA
11
16
0)
Load immediate shifted.
16 0)
(RT) (IM
Extended mnemonic for
addis RT,0,IM
16 0) from (RA|0).
Subtract (IM
Place result in RT.
Extended mnemonic for
addis RT,RA, IM
PPC440x5 CPU Core User's Manual
16
Function
addis
Add Immediate Shifted
IM
Other Registers
Altered
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